1. Field of the invention
The present invention relates to a TTL-compatible cell to be included as signal input circuit in integrated electronic circuits in CMOS technology, to provide the CMOS chip with compatibility with TTL logics. More particularly, the invention relates to a TTL-compatible cell with nil power dissipation during the power-down of the integrated circuit.
2. Prior Art
As is known, very large scale integration (VLSI) electronic integrated circuits are often produced in CMOS technology to have low power dissipation. To further reduce the average power consumption it is also known to provide said CMOS chips with a deactivation or power-down pin, by enabling which one acts in a known manner on the chip to drastically lower the dissipation of the circuit (down to practically zero values) when the chip is not used, though power is still supplied thereto.
However, many input pins of the CMOS chip are required to be compatible with signals in TTL logic: this means that the input circuit to which the pin leads must recognize as logical 0 any voltage lower than 0.8 V, and as logical 1 any voltage above 2.0 V (sometimes 2.4 V). For this purpose an input circuit is used, known as "TTL-compatible cell", which must supply in output corresponding CMOS levels respectively of logical 0 and logical 1.
TTL-compatible cells of the prior art are substantially constituted by two cascade coupled inverters, the first whereof has a tripping threshold (for example 1.4 V) appropriate for discriminating between the abovesaid two TTL logic levels.
In power-down conditions, the consumption of said cell may remain relatively high since, as will be better explained hereinafter, there are intermediate levels of the TTL input signal (which is not under the control of the CMOS chip) such that a conductive path exists in the input inverter of the cell between the power supply and the ground, and therefore an amount of power appreciable if compared to the extremely low dissipations of the other elements of the chip is dissipated.
In known TTL-compatible cells the problem is solved, as will be explained in greater detail hereinafter, by providing the cell with a MOS transistor controlled by the inverter to force the TTL logic external to the chip so as to make its voltage vary to extreme values, such as to bring said inverter to non-dissipative conditions.
This solution, however, has the disadvantage of modifying the conditions of the external TTL logic, and this in certain cases is unacceptable, for example when the external TTL logic also drives other circuits. Furthermore, the solution is ineffective when the external logic is a voltage generator.